Principal Signoff CAD Engineer

Microsoft is a global technology company that creates software, cloud services, hardware and enterprise solutions used by businesses and consumers worldwide. In its Silicon Engineering group, the Principal Signoff CAD Engineer works on the final verification stages of integrated‑circuit design, ensuring that layout data meets all manufacturing and electrical requirements before tape‑out. Day‑to‑day responsibilities include running design‑rule checks, layout‑vs‑schematic comparisons, timing and power signoff flows, debugging violations, and collaborating with physical‑design, layout and test teams to resolve issues. The role also involves maintaining signoff decks, updating checklists, and mentoring junior engineers on best practices for CAD signoff. This position suits experienced VLSI engineers with deep knowledge of signoff criteria, proficiency with Cadence or Synopsys signoff tools, and a track record of delivering clean tape‑outs for complex SoCs or ASICs in a fast‑paced semiconductor environment.