Senior Design Verification Engineer

Microsoft is a global technology company that designs and produces a wide range of hardware and software products, including silicon chips for cloud infrastructure, consumer devices and enterprise solutions. As a Senior Design Verification Engineer within its Silicon Engineering group, you will be responsible for ensuring that ASIC and FPGA designs meet functional specifications before tape‑out. Day‑to‑day work includes writing SystemVerilog testbenches, developing UVM‑based verification environments, running regression simulations, debugging failures, and collaborating with RTL designers to clarify intent and improve coverage. You will also participate in formal verification, coverage‑driven testing, and post‑silicon validation activities, helping to drive sign‑off quality metrics. The role suits engineers with several years of experience in ASIC/FPGA verification, strong proficiency in SystemVerilog and UVM, familiarity with simulation tools such as VCS or Questa, and a solid understanding of digital design concepts. Candidates who are detail‑oriented, comfortable working in a multidisciplinary team, and eager to tackle complex silicon challenges will find this position a good fit.